The present invention relates to a pattern length measurement method and apparatus and a computer program for performing pattern length measurement. More particularly but not exclusively, this invention relates to a method and apparatus for measuring dimensions of a pattern by comparison between design data of the pattern and a real image thereof.
It is known that a pattern on semiconductor integrated circuitry is measured using computer-aided design (CAD) data. Design data such as CAD data is the one that indicates the inherently expected “ideal” shape of a semiconductor circuit element; thus, comparing the CAD data to an actually formed pattern makes it possible to evaluate a semiconductor device fabrication process. JP-A-2001-338304 (corresponding to U.S. Pat. No. 6,868,175) discloses therein a technique for performing edge detection of a pattern to be inspected and a reference pattern and for comparing detected edges together to thereby detect a deformation amount of the pattern relative to the design data.
Nowadays, semiconductor integrated circuits further advance both in miniaturization and in multilayer structure complexity, resulting in likewise improvement in performance of semiconductor device inspection apparatus. One of such semiconductor inspection apparatus is a critical dimension scanning electron microscope (CD-SEM). CD-SEM is an apparatus of the type which measures the size of a pattern formed on a workpiece based on secondary electrons obtained by scanning an electron beam on the workpiece of interest. In JP-A-2001-338304 (U.S. Pat. No. 6,868,175), it is disclosed that a pattern image formed by CD-SEM or the like is compared with its CAD data to thereby detect a deformation amount of the pattern. Unfortunately, this approach suffers from problems which follow.
On a semiconductor wafer, a large number of patterns are formed to constitute on-chip semiconductor circuit elements, such as transistors for example. For each semiconductor circuit element, its size and the dimension of a contact/junction area between patterns are determined in such a way as to realize specified performance at the stage of semiconductor device designs.
Unfortunately, the prior technique approach as taught by JP-A-2001-338304 (U.S. Pat. No. 6,868,175) is not satisfactory for performing measurement of the currently existing complicated multilayered circuit elements. One reason of this is that the prior technique approach disclosed in this Japanese patent bulletin is silent about the efficiency-increased measurement in terms of the measurement of a semiconductor circuit element with a great number of length measurement points being settable thereon due to the complexity thereof. Another reason is that the prior technique approach fails to take into consideration the fact that a semiconductor circuit element is formed to span more than two stacked layers.